Lower = more efficient. World best: ~65× (Apple M3). x86 best: ~570× (Intel 285K, 2024).
Efficiency Class
STANDARD
Current x86 flagship class
Global rank: 5 of 7 chips in database
SCAPE Competitive Index
165×Apple M3 (2023)
268×Apple M4 (2024)
3316×Snapdragon X Elite (2024)
4570×Intel Core Ultra 9 285K (2024)
5576×AMD Ryzen 9 9950X ◀
61,326×NVIDIA H200 SXM (2024)
71,435×NVIDIA H100 SXM5 (2022)
Global Ranking — All Platforms
SCAPE Thermal Analysis — Efficiency Across Full Junction Temperature Range
n = [proprietary]. Derived from published specifications only. Internal thermal data can verify each row independently.
Tj (°C)
SCAPE Index
p/transistor (fJ)
Notes
20°C
543.3×
0.001524
40°C
555.6×
0.001665
55°C
564.5×
0.001773
← target Tj
70°C
573.2×
0.001882
75°C
576×
0.001919
← published anchor
85°C
581.6×
0.001993
95°C
587.1×
0.002068
100°C
589.8×
0.002106
105°C
592.4×
0.002144
TjMax
Thermal Curve — A(T) = A_ref × (T/T_ref)^n · AMD n = [proprietary] vs Intel n = [proprietary] · Crossover ~82°C
AMD vs Intel Crossover Analysis
AMD 9950X vs Intel 285K — Published anchor: 75°C
At 75°C (nominal): AMD 576× vs Intel 570× — gap < 1%
At 40°C (excellent cooling): AMD 556× vs Intel 516× — Intel leads by 8%
At 105°C (TjMax, sustained load): AMD 592× vs Intel 616× — AMD leads by 4%
Crossover: ~82°C — Intel more efficient below, AMD more efficient above.
Data center AI inference runs at 80–100°C under sustained load. AMD wins that regime. Derived from three published numbers. Does not appear in any published benchmark.
SCAPE Technical Assessment
CURRENT X86 FRONTIER: SCAPE index 576×. This chip is in the x86 flagship efficiency class — where AMD Zen5 and Intel Arrow Lake converge in 2024. The AMD-Intel efficiency lead that existed from 2017 to 2022 has closed to less than 1% at the 4nm node.
Architecture class: Post-Dennard AMD. Chiplet architecture enables faster efficiency improvement than Intel at the same foundry node. AMD held a 3.7× efficiency lead over Intel at peak (2020) — that lead has closed to less than 1% at 4nm. SCAPE projects Intel overtaking AMD at 2nm (~2027).
SCAPE Recommendations
DENNARD TRANSITION: The SCAPE framework predicts the next regime change at 2026–2028. Per-node efficiency improvement at 2nm will be materially below the Arrow Lake 70.7% step. SCAPE quantifies the four levers available when node shrinks stop delivering: architecture redesign, chiplet specialization, thermal operating regime optimization, and workload-specific scheduler tuning.
AMD THERMAL ADVANTAGE: At 105°C TjMax AMD leads Intel by 4%. The crossover is 82°C. Most sustained data center AI inference runs above 80°C. AMD already wins that workload.
SCAPE Core Metrics
SCAPE Index (A)576×dimensionless; lower = better
TDP170 Wpublished
Transistor count20.6 Bpublished
Base clock frequency4.3 GHzpublished
Junction temperature (anchor)75°Cnominal operating
Derived Values
Switching energy / transistor0.001919 fJat anchor Tj
Thermodynamic floor at Tj[proprietary]IAM reference floor at operating temperature
Global SCAPE rank5 of 7
Temperature Predictions
SCAPE index at 40°C555.6×IAM prediction
SCAPE index at 75°C576×published anchor
SCAPE index at 105°C592.4×IAM prediction — TjMax
Trajectory & Roadmap
Improvement rate (per node)33.5%validated from 20-yr dataset
Projected index — 2028112.6×at current rate
Projected index — 203222×at current rate
Apple-class parity year2029.2projected at current rate
Workload Suitability Ranking
● Video / Media EncodeRank 1Excellent — low branch misprediction penalty
Every chip's total efficiency gap separates into three independent portions. Only one is reachable by engineering investment. Patent Applications 64/012,720 and 64/014,568.
Locked 12.2%
Engineering-Accessible 87.8%
Architecture-locked12.2% (70×)ISA overhead — only ISA redesign moves this
Engineering-accessible87.8% (506×)What every node shrink, chiplet, and micro-arch improvement addresses
⬡ Switching Energy Reserve — AMD Ryzen 9 9950X
SCAPE Index
576×
switching energy ratio
SER Tier
OPEN RUNWAY
substantial runway remains
Quadrant
FAB OPPORTUNITY
physics has room
E_sw / transistor
0.001919 fJ
Floor: 0.000003 fJ
FAB OPPORTUNITY: Behind on competitive index but with significant physical runway remaining. The physics still has room. The gap to the leader is closeable. Node shrinks and architectural improvements both move the needle here. Priority: accelerate per-node efficiency improvement rate.
Projected Index at Future Nodes
Year
Node
Projected SCAPE Index
Note
2024 ← now
4nm
576×
2026
2nm
383×
2027
2nm
255×
2028
1.5nm
169×
★ Dennard signal?
2030
1nm
113×
2032
0.7nm
75×
approaching floor
Efficiency Levers — When Node Shrinks Are Not Enough
Architecture Efficiency MODERATE
SCAPE index moves from 576× to ~489×. Pipeline and ISA optimisation independent of node shrink.
Next Node Shrink HIGH
SCAPE index moves from 576× to 383×. Derived from validated 33.5% per-node improvement rate.
Thermal Regime — Sustained 85°C LOW–MOD
At 85°C: 581.6×. At 105°C: 592.4×. Architecture-specific thermal response n = [proprietary].
Chiplet Specialisation MODERATE
System-level SCAPE index moves from 576× to 518×. Estimated 10% system gain from separating compute and I/O dies at optimal nodes.
SER derived from published specifications. Trajectory from validated per-node improvement rate. Patent Applications 64/012,720 and 64/014,568.
⚡ Transition Detection — AMD Ryzen 9 9950X
Regime Status
APPROACHING
transition window opening
Actual per-node improvement
33.2%
Dennard baseline: 72%
% of Dennard delivered
46.2%
5nm → 4nm
Dennard Amplifier
g = 2.17×
DENNARD GAP OPENING
What this means: Dennard scaling promised 72% improvement per node step. This architecture delivered 33.2%. Each successive node step now requires 2.17× the engineering effort of the pre-2005 era to match the original Dennard efficiency trajectory. The Amplifier quantifies how far the industry has drifted from the free-scaling era.
Efficiency improvement this node (33.2%) is 46% of the Dennard baseline. Improvement rate is decelerating. The transition window is opening. The SCAPE framework identified the 2005 transition at this same signal level.
Transition window: 1–2 node generations. Projected 2026–2028.
SCAPE index: 4nm node 576× vs prior 5nm node 862.9×. Dennard scaling would have predicted 241.6×. Efficiency gap: 2.39× — the improvement Dennard promised that did not arrive.
Escape Routes — What To Do When Node Shrinks Stop Delivering
Architecture Redesign HIGH
Adopting ARM-class instruction efficiency moves index from 576× to approximately 334×. Apple Silicon architecture class: 65–68×. Independent of process node — AMD and Apple share the same TSMC foundry at 3nm.
Thermal Operating Regime MODERATE
At 40°C: 556×. At 105°C: 592×. Workload routing to the correct thermal regime delivers measurable gains. AI inference at sustained high temperature favours architectures with lower hot-side degradation.
Chiplet Specialisation MODERATE
Separating compute and I/O dies at optimised nodes projects system-level index to approximately 507×. Each die operates at its own efficiency optimum rather than the monolithic compromise.
Workload-Specific Scheduling LOW–MOD
x86 overhead is largest in irregular workloads with high branch misprediction. Dense compute — matrix operations, large-batch AI inference — minimises this overhead. Directing the right workloads to the right cores at the right thermal point turns a SCAPE measurement into a scheduling specification.
Detection derived from published specifications at two node generations. Prior generation pre-populated from verified dataset. Patent Applications 64/012,720 and 64/014,568.
◈ Signal Integrity Analysis — AMD Ryzen 9 9950X
Signal Integrity Tier
ROBUST
SNM at TjMax: 175.7 mV (97.6%)
PI / SI Bottleneck
POWER LIMITED
SCAPE Index: 576×
Low-Frequency Noise
NEGLIGIBLE
4.3 GHz operating
POWER LIMITED: Signal integrity is healthy but switching efficiency is the constraint. The bottleneck is Power Integrity, not Signal Integrity. Priority: architectural efficiency improvements — instruction pipeline, voltage scaling, clock gating strategy.
Operating frequency 4300 MHz is well above the 1/f corner frequency range. Thermal noise dominates. Low-frequency noise is not the primary signal integrity concern at this operating point.
Static Noise Margin vs Junction Temperature
Nominal SNM: 180 mV · VDD: 1.1 V · Node: 4nm
Junction Temp
Static Noise Margin
Budget Remaining
20°C
180 mV
100%
40°C
180 mV
100%
55°C
180 mV
100%
75°C ★ anchor
180 mV
100%
85°C
178.6 mV
99.2%
95°C
177.1 mV
98.4%
100°C
176.4 mV
98.0%
105°C
175.7 mV
97.6%
Signal integrity analysis derived from published VDD and process node specifications. Johnson-Nyquist thermal noise model. Patent Applications 64/012,720 and 64/014,568.
◎ Strategic Target — AI Inference vs Intel Core Ultra 9 285K by 2028
Trajectory Status
BEHIND
Intel improving faster
Gap to lead (2028)
50.5×
you: 112.6× · Intel: 62.1×
Gap closes
2029.5
at current rates
Intel's 41% per-node improvement rate outpaces AMD's 33.5% at 2nm. At current rates, Intel leads AMD by 2028 for AI Inference. Below 82°C Intel's higher temperature sensitivity (n = [proprietary]) gives it an edge in cold-running deployments. To lead Intel by 2028 for AI Inference at sustained load, AMD would need to reach A ≈ 62× — achievable only through ISA redesign or node acceleration.
AMD retains the thermal advantage above 82°C — the regime where AI inference workloads actually run at scale.
Capital Allocation — Escape Routes Ranked by Impact
Junction Load Optimisation HIGH
Sustained >80°C operating regime favours AMD architecture class. Scheduler and workload routing changes. Lowest capital requirement.
Architecture Pipeline Redesign HIGH
Instruction fetch reduction and speculative execution pruning. Medium capital, 18–24 month cycle.
Process Node Acceleration MEDIUM
Node shrink delivers improvement per validated rate. High capital, 24–36 month cycle.
Chiplet Integration Strategy MEDIUM
Disaggregation of compute and memory dies. Addresses memory bandwidth ceiling for inference batch size.
Analysis derived from published specifications and validated improvement rates. Patent Applications 64/012,720 and 64/014,568.
Every chip's total efficiency gap separates into three independent portions. Only one is reachable by engineering investment. Patent Applications 64/012,720 and 64/014,568.
Locked 12.2%
Engineering-Accessible 87.8%
Architecture-locked12.2% (70×)ISA overhead — only ISA redesign moves this
Engineering-accessible87.8% (506×)What every node shrink, chiplet, and micro-arch improvement addresses
Dennard Transition Analysis — 5nm → 4nm
Prior SCAPE
862.9×
5nm prior gen
Current SCAPE
576×
4nm this gen
Actual step rate
33.2%
vs Dennard 72%
Regime
APPROACHING
46% of baseline
Dennard predicted index241.6×what 72% improvement would give
Actual achieved index576×what was delivered
Efficiency gap (actual ÷ predicted)2.39×improvement Dennard promised that did not arrive
Observed Dennard Amplifier g2.17× — this specific transitionDERIVED from 5nm→4nm step
Temperature Analysis — Target Tj: 55°C
Tj (°C)
SCAPE Index
vs anchor
Note
20°C
543.3×
-5.7%
40°C
555.6×
-3.5%
55°C
564.5×
-2.0%
← target Tj
75°C
576×
—
← anchor
85°C
581.6×
+1.0%
105°C
592.4×
+2.9%
TjMax
Forward Translation — What Specifications Reach SCAPE 300×?
Gap to target
1.92×
current ÷ target
Required TDP
88.5 W
at current trans + freq
Required transistors
39.5 B
at current TDP + freq
These are the published specifications that would need to be achieved to reach SCAPE 300×, holding all other inputs constant. Each result is independently verifiable from the three published inputs alone. Not a projection — a constraint equation. ~1.6 node steps at current improvement rate.
ISA Escape Scenario — ARM ISA (data-center class)
Current — x86
Architectural floor[proprietary]ISA minimum
Distance above floor8.23×concern: LOW
ISA overhead fraction12.2%irreducible
After ISA Change — ARM
New architectural floor[proprietary]ARM minimum
New distance above floor16.46×concern: LOW
New ISA overhead fraction6.1%half of current overhead
Chiplet Separation Scenario
Current SCAPE
576×
monolithic die
After chiplet
518×
I/O + compute separated
New floor ratio
7.4×
same architectural floor
Estimated 10% system-level efficiency gain from separating I/O and compute dies at their optimal process nodes. Architecture-agnostic — applies at any node. Does not move the architectural floor.
SCAPE Engineering Diagnostic · Informational Actualization Model (IAM) · Mahaffey (2026) All derived values computed from published inputs only. IAM reference floor and architectural floors are proprietary. Patent Applications 64/012,720 and 64/014,568. All commercial terms through legal counsel.